Integration of NIOS II with VHDL File

[nliaqat]

I'm trying to integrate a NIOS II processor with my VHDL design to perform matrix operations using alpha angle inputs. First, I’m using two constant angles to test the integration, but the angle values are not being passed in the VHDL file, so I can’t get the output. These two angles are used in the main VHDL file to generate the shifted PWM. I’ve seen some posts related to this but couldn’t find my desired answer. Can someone guide me on how to solve this issue or share any relevant posts or examples?"count the characters"

 

[FvM]

Interesting part isn't visible in the post, we need to read the project files. Not sure if I find the time.

Reset wiring in Platform Designer looks wrong at first sight.

Sending two numbers through conduit is basically a simple task.

 

[nliaqat]

Interesting part isn't visible in the post, we need to read the project files. Not sure if I find the time.

Reset wiring in Platform Designer looks wrong at first sight.

Sending two numbers through conduit is basically a simple task.

Thanks, Can you provide me any material and videos.

 

[std_match]

Does it work if you put the constants in the VHDL file?

 

[nliaqat]

Does it work if you put the constants in the VHDL file?

Yes, it works when i assign the simple angel in vhdl file.

 

[FvM]

I'm familiar with Quartus Platform Designer, but not using Nios II soft processor.

Sure that your processor is running at all? How do you load executable code (.elf file), via debugger?

 

[nliaqat]

I'm familiar with Quartus Platform Designer, but not using Nios II soft processor.

Sure that your processor is running at all? How do you load executable code (.elf file), via debugger?

I’m new to the field of FPGA. I’m just trying to understand how these things work. Maybe I didn’t added the file — I’ll try to add it and then update you. Many thanks!

 

[FvM]

Regarding post #2, I compared reset wiring with existing Nios II design, it's almost o.k., but reset input of clock/reset block should be exported and driven by global reset, not connected in a loop with debug_reset_request.