module coarsetiming( clk,
rst,
valid_in,
in_real,
in_imag,
valid_out,
out_real,
out_imag);
input clk; // Clock
input rst; // System reset
input valid_in; // Valid signal for input data
input signed [15:0] in_real; // Real part of input data
input signed [15:0] in_imag; // Imaginary part of input data
output reg valid_out; // Valid signal for output data
output reg signed [15:0] out_real; // Real part of output data
output reg signed [15:0] out_imag; // Imaginary part of output data
// Variable Declarations
reg signed [15:0] RxBuffer_real[87:0];
reg signed [15:0] RxBuffer_imag[87:0];
reg [8:0] count;
reg [6:0] CorrCount;
reg [6:0] CorrIndex;
reg [38:0] CorrMagMax;
reg signed [19:0] Corrreal;
reg signed [19:0] Corrimag;
// Buffering the input samples for the next block
always @(`CLK_EDGE clk or `RESET_EDGE rst) begin
if (rst == `RESET_ON) begin
out_real <= 0;
out_imag <= 0;
end
else if (valid_in == 1) begin
out_real <= in_real;
out_imag <= in_imag;
end
end
wire [38:0] CorrMag;
assign CorrMag = Corrreal*Corrreal + Corrimag*Corrimag;
// Performing Synchronization
always @(`CLK_EDGE clk or `RESET_EDGE rst) begin
if (rst == `RESET_ON) begin
count <= 0;
CorrCount <= 0;
Corrreal <= 0;
Corrimag <= 0;
CorrMagMax <= 0;
CorrIndex <= 0;
valid_out <= 0;
end
else if (valid_in == 1) begin
if (count > 40 && CorrCount < 45) begin
Corrreal <= RxBuffer_real[CorrCount] + RxBuffer_real[CorrCount+4] + RxBuffer_real[CorrCount+8] - RxBuffer_real[CorrCount+12] -
RxBuffer_real[CorrCount+16] - RxBuffer_real[CorrCount+20] + RxBuffer_real[CorrCount+24] - RxBuffer_real[CorrCount+28] -
RxBuffer_real[CorrCount+32] + RxBuffer_real[CorrCount+36] - RxBuffer_real[CorrCount+40];
Corrimag <= RxBuffer_imag[CorrCount] + RxBuffer_imag[CorrCount+4] + RxBuffer_imag[CorrCount+8] - RxBuffer_imag[CorrCount+12] -
RxBuffer_imag[CorrCount+16] - RxBuffer_imag[CorrCount+20] + RxBuffer_imag[CorrCount+24] - RxBuffer_imag[CorrCount+28] -
RxBuffer_imag[CorrCount+32] + RxBuffer_imag[CorrCount+36] - RxBuffer_imag[CorrCount+40];
CorrCount <= CorrCount + 6'd1;
if (CorrMag > CorrMagMax) begin
CorrIndex <= CorrCount-6'd1;
CorrMagMax <= CorrMag;
end
RxBuffer_real[count] <= in_real;
RxBuffer_imag[count] <= in_imag;
count <= count + 6'd1;
end
else if (count >= CorrIndex+88) begin
valid_out <= 1;
end
else begin
RxBuffer_real[count] <= in_real;
RxBuffer_imag[count] <= in_imag;
count <= count + 6'd1;
end
end
else begin
valid_out <= 0;
end
end
endmodule