Integer multiplication

Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use ieee.numeric_std.all;
 
architecture arch of bch_syndrome is
    signal e1:std_logic_vector(15 downto 0);
    signal b1:std_logic_vector(15 downto 0);
    signal c1:integer;--unsigned(15 downto 0);
    signal f1:integer range 0 to 65536;
    signal d1:integer;--unsigned(31 downto 0);
    signal syndromesum1:integer; 
    signal i1:integer range 0 to 65535;
    signal j1:integer range 0 to 32400;
 
begin 
process(reset,clk,count)
    variable a1:std_logic_vector(15 downto 0);
    begin
      if(clk'event and clk= '1') then
      if(reset='1')then
        i1<=0;
        j1<=32400;
        b1<=(others=>'0');
        c1<=0;
        d1<=0;
        a1:=(others=>'0');
        e1<=(others=>'0');
        syndromesum1<=0;
else
           e1<=(e1(14 downto 0)& DataIn1(j1));
            b1<=a1 xor e1;
            c1<= conv_INTEGER(b1);
            f1<= alpha_value(i1);
            d1<=f1*c1;
            syndromesum1<=syndromesum1+d1;
            a1:=conv_STD_LOGIC_VECTOR(d1, 16);                                               
            d1<=0;
            j1<=j1-1;
        end if;
        end if;
    end process;