rettylee
Newbie level 6
A verilog behavior model problem....
Hi,guys:
I want to add jitter to a signal clk.When using random generator task,I need integer data as seed in always block like this:
integer seed;
real d;
always begin
@(posedge clk);
seed = $random;
d = $dist_normal(seed,0,1)/1000.0;
# d ;
clk_out = 1;
@(negedge clk);
..........(like before)
clk_out = 0;
end
But after simulation,I found that seed changed not all with the posedge of clk,some of them changed not at the posedge of clk.I am confused. Is the problem from integer assign ? or my method have problems....
Thank you for your guide !
Hi,guys:
I want to add jitter to a signal clk.When using random generator task,I need integer data as seed in always block like this:
integer seed;
real d;
always begin
@(posedge clk);
seed = $random;
d = $dist_normal(seed,0,1)/1000.0;
# d ;
clk_out = 1;
@(negedge clk);
..........(like before)
clk_out = 0;
end
But after simulation,I found that seed changed not all with the posedge of clk,some of them changed not at the posedge of clk.I am confused. Is the problem from integer assign ? or my method have problems....
Thank you for your guide !
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