Instantiating problem in Vhdl division while using component

Code VHDL - [expand]
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LIBRARY ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
 
ENTITY computus IS
  port(CLK : in bit;
    year : in unsigned(11 downto 0);
    April : out bit;
    day: out unsigned (4 downto 0));
    
END  computus;
 
--
ARCHITECTURE structure OF computus IS
  component a_div 
    port(CLK, St: in bit;
      Dbus: in unsigned(15 downto 0);
      Quotient: out unsigned(15 downto 0);
      Remainder : out unsigned(15 downto 0);
      V, Rdy : out bit);
end component;
 
 
  signal State : integer range 0 to 6;
  signal Count : unsigned(3 downto 0);
  signal Sign, C, Cm2 : bit;
  signal Sum, Compout : unsigned(15 downto 0);
  signal Dividend: unsigned(31 downto 0);
  constant Divisor: std_logic_vector(15 downto 0):= X"13";
  alias Acc: unsigned( 15 downto 0) is Dividend(31 downto  12);
  
  begin
   a0:a_div port map (year(0),Compout(0),Divisor(0),Dividend(0));
   a1:a_div port map (year(1),Compout(1),Divisor(1),Dividend(1));
    a2:a_div port map (year(2),Compout(2),Divisor(2),Dividend(2));
    a3: a_div port map (year(3),Compout(3),Divisor(3),Dividend(3));
    a4:a_div port map (year(4),Compout(4),Divisor(4),Dividend(4));
    a5:a_div port map (year(5),Compout(5),Divisor(5),Dividend(5));
    a6: a_div port map (year(6),Compout(6),Divisor(6),Dividend(6));
    a7:a_div port map(year(7),Compout(7),Divisor(7),Dividend(7));
    a8:a_div port map(year(8),Compout(8), Divisor(8),Dividend(8));
    a9:a_div port map(year(9),Compout(9),Divisor(9),Dividend(9));
    a10:a_div port map(year(10),Compout(10),Divisor(10),Dividend(10));
    a11:a_div port map(year(11),Compout(11),Divisor(11),Dividend(11));
    
   
   
    
    process(CLK)
    begin
    if CLK'event and CLK = '1'then
      case State is
          when 0 =>
            if St = '1' then
              Acc <= Dbus;
              Sign <= Dbus(15);
              State <= 1;
              V <= '0';
              Count <= "0000";
            end if;
            when 1 =>
              Dividend (15 downto 0) <= Dbus;
              State <= 2;
            when 2 =>
              Divisor <= Dbus;
              if Sign = '1' then
                dividend <= not dividend + 1;
              end if;
              State <= 3;
            when 3 =>
              Dividend <= Dividend(30 downto 0) & '0';
              Count <= Count + 1;  State <= 4;
            when 4 =>
              if C = '1' then
                v <= '1'; State <= 0;
              else
                Dividend <= Dividend(30 downto 0) & '0';
                Count <= Count + 1; State <= 5;
              end if;
            when 5 =>
              if C = '1' then
                ACC <= Sum;
                dividend(0) <= '1';
              else
                Dividend <= Dividend(30 downto 0) & '0';
                if Count = 15 then State <= 6; end if;
                Count <= Count + 1;
              end if;
            when 6 =>
              State <= 0;
              if C = '1' then
                Acc <= Sum;
                dividend(0) <= '1'; State <=6;
                elsif (Sign xor Divisor(15)) = '1' then
                  Dividend <= not Dividend + 1;
                end if;
          end case;
        end if;  
    end process;
     Cm2 <= not divisor;
    compout <= divisor when Cm2 = '0'
      else not divisor;
    Sum <= Acc + compout + unsigned'(0=>Cm2);
    C <= not Sum(15);
    Quotient <= Dividend(15 downto 0);
    Remainder <= Dividend(31 downto 16);
    Rdy <= '1' when State = 0 else '0';
    
  end structure;