kel8157
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meters?
Let's say I wish to instantiate a RAM verilog model, which uses a init file in the parameter..
How do I change this filename in my VHDL file?
I use ncsim 8+..
Let's say I wish to instantiate a RAM verilog model, which uses a init file in the parameter..
How do I change this filename in my VHDL file?
I use ncsim 8+..