I'm doing a project about multi-power design.
ex:
Two power plane : VDD1 and VDD2. VDD1 sometimes power-off and VDD2 is always on.
I need to insert isolation cell between VDD1 and VDD2 interface. But I can't find isolation cell on standard cell library.
Does it mean I should create isolation cell by myself?
in my thought, below 90nm process, there have ISO cells etc in the library. most these ISO cell ans same as AND or OR gate, I think you can refer to these two cells and create a new ISO for your use.