kimilee
Newbie
In the timing summary report, I see that there is no in2out path reported (N/A).
Then I do report_timing -path_group in2out and it shows unconstrained too.
I did set_input_delay and set_output_delay to all input and output ports relative to the main clk.
If that is the case, how can I determine if there is really any input port -> combo logic -> output port in the design,
since report_timing keeps reporting it as unconstrained.
Then I do report_timing -path_group in2out and it shows unconstrained too.
I did set_input_delay and set_output_delay to all input and output ports relative to the main clk.
If that is the case, how can I determine if there is really any input port -> combo logic -> output port in the design,
since report_timing keeps reporting it as unconstrained.