Input test vector is not loaded in the Questa

[mohamis288]

Hello,

I have written testbench for my project. All the input files including netlist.v, netlist.sdf and testbench.v were compiled correctly (but there is some warnning). But when I simulate, it seems data are not read at the input. I put the requirement here:

testbench file:

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

// Module Name: FIR_TB



module FIR_TestBench;

parameter N = 8;

reg clk, reset;
reg [N-1:0] my_data_in;
wire [N-1:0] my_data_out;

FIR_Filter uut(.clk(clk), .reset(reset), .my_data_in(my_data_in), .my_data_out(my_data_out));



// input sine wave data
initial
$readmemb("signal.data", RAMM);

// Create the RAM
reg [N-1:0] RAMM [31:0];

// create a clock
initial
clk = 0;
reg [4:0] Address_me;

always
#10 clk = ~ clk; 

// Read RAMM data and give to design
always@(posedge clk)
    my_data_in <= RAMM[Address_me];
    
// Address_me counter

initial
Address_me = 1;
always@(posedge clk)
begin
    if (Address_me == 31)
        Address_me = 0;
    else
        Address_me = Address_me + 1;
end     

endmodule

as you can see in the above code, I have read the 'signal.data' file and then I put it in the RAM. 'Signal.data' file is in the same folder as the testbench file.

here is a couple of line in the testbench file:

00001111
00010100
00010001
00010011
00011011
00100111
00011111
00100110
00011110
00101111
00110100
00111001
00111100
00111010
00111010
00110111
00101100
00111100
00110010
00110000
00110011
00110110
00100101
00100101
00100010
00101001
00010111

the warnning in the log window is here:

 Loading instances from /home/user1/CAD/final/netlist2.sdf
# Loading timing data from /home/user1/CAD/final/netlist2.sdf
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(236): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/U153/A2'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(238): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/U152/A2'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(240): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/U151/A2'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(249): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/U145/A1'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(253): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/U144/C'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(331): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/add_2_root_add_51_6/U1_2/B'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(339): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/add_2_root_add_51_6/U2/A1'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(341): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/add_2_root_add_51_6/U1/A1'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(463): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/DFF0/\data_delayed_reg[0] /D'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-SDF-16107) /home/user1/CAD/final/netlist2.sdf(466): The interconnect '/FIR_TestBench/uut/my_data_in' is not connected to the destination '/FIR_TestBench/uut/DFF0/\data_delayed_reg[1] /D'.
# The interconnect request will be replaced with a port annotation at the destination.
# ** Warning: (vsim-8756) Instance 'FIR_TestBench.uut.\my_data_out_reg[7] ' - Negative timing check limits detected in simulation with cells modeled without delayed copies of data or reference signals.
#    Time: 0 ps  Iteration: 0  Instance: /FIR_TestBench File: /home/user1/CAD/Lib/tcbn65lp.v Line: 13690
# ** Warning: (vsim-3448) /home/user1/CAD/final/netlist2.sdf(2907): Timing check limit can not be negative. Setting negative check constraint (-50 ps) to zero.
# ** Warning: (vsim-3448) /home/user1/CAD/final/netlist2.sdf(2908): Timing check limit can not be negative. Setting negative check constraint (-50 ps) to zero.
# ** Warning: (vsim-3448) /home/user1/CAD/final/netlist2.sdf(2908): Timing check limit can not be negative. Setting negative check constraint (-50 ps) to zero.
# ** Warning: (vsim-3448) /home/user1/CAD/final/netlist2.sdf(2931): Timing check limit can not be negative. Setting negative check constraint (-50 ps) to zero.
# ** Warning: (vsim-3448) /home/user1/CAD/final/netlist2.sdf(2932): Timing check limit can not be negative. Setting negative check constraint (-50 ps) to zero.
.
.
.
.

 

[barry]

Have you verified that the data is, in fact, read into RAM?
Have you verified that my_data_in is getting data?
The warning messages seem to point to an error in your UUT, not necessarily in your testbench.

 

[mohamis288]

this was solved. I just need to replace the complete address of 'signal.Data' file.