Input offset voltage of 2 stage opamp.

Hi Everyone,
I am trying to simulate a two stage opamp (NMOS input). I am not concerned about random offset (for now I am only trying to fix systematic offset). I have the following question:

If I size the MOSFETs "perfectly" so that the bias current is exactly split between the input pair, should I still get a systematic offset? I have attached a figure in the post for your reference. I have tied sizing the MOSFETs according to what the text book says. When I apply a CM voltage of 900 mV, my output transistor (NMOS load - MN4) still remains in triode region - could anybody please explain why this happening?

Thanks for any replies.

For balanced output, MN4 must be half the area of MN0.

FvM said:

For balanced output, MN4 must be half the area of MN0.

Click to expand...

Thank you for your reply, caould you please explain a little as to why MN4 wouldve to be half the area of MN0?

Consider current splitting.

Thank you once again. Here is the logic I used:

Lets assume MN0 is carrying 1uA. Since MN4 is sized similar, it'll also carry 1uA. The 1uA splits between MP1 and MP2 which get 500nA each. Since MP3 (output PMOS) gets all of the 1uA, it should be sized at twice the width of MP1/MP2 to have the same overdrive voltage. (as you can see mp1/2 are sized at W=2.4u and mp3 is sized at w=4.8u).

Am I right or did I make a mistake somewhere in there?

Yes, I didn't noticed double width of MP3.

You should monitor operation points of all transistors and also determine the actual input offset.

There will be still a certain inbalance due to different Vds.

First of all You should simulating this OPAMP in closed loop, i.e. as bufer. To minimalize systematic offset You also should have the same finger width in current mirrors.

saqib.shah06 said:

When I apply a CM voltage of 900 mV, my output transistor (NMOS load - MN4) still remains in triode region

Click to expand...

What are the threshold voltages of your process? Is it a 180nm process?

For our (low Vth, fast) 180nm process your design shows quite reasonable operating points:

erikl said:

What are the threshold voltages of your process? Is it a 180nm process?

For our (low Vth, fast) 180nm process your design shows quite reasonable operating points:

Click to expand...

Thank you for your reply. This is a CSM .35um process. Threshold is around 400mV. I tried by reducing the current in the output stage to 1/2 and changing the output PMOS sizing to half of the original as well (4.8u/2 = 2.4u). In this case the circuit works fine and all the transistors are in saturation - Any ideas?