inout ports in verilog

kaelk · Feb 12, 2014

Dear all;

I have the following error with modelsim

Error: module_uart/biDirBuffer.sv(6): An inout port (dat_io) must be a net type.

ad the code for the moule is below

Code Verilog - [expand]
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module biDirBuffer(
   input  logic       outEn,
   input  logic [7:0] dat_i,
   output logic [7:0] dat_o,
   inout  logic  [7:0] dat_io
);
   
   assign dat_o = dat_io; 
   assign dat_io = outEn ? dat_i : 'Z;
endmodule

I think that I made he correct assignments, if you have any idea please help
Thanks

mrflibble · Feb 12, 2014

Try "inout wire [7:0] dat_io" or just plain "inout [7:0] dat_io" instead. Because, well, an inout port (dat_io) must be a net type. The error message says it all really.

kaelk · Feb 12, 2014

mrflibble said:
Try "inout wire [7:0] dat_io" or just plain "inout [7:0] dat_io" instead. Because, well, an inout port (dat_io) must be a net type. The error message says it all really.

thanks mrflibble, I tried it and it works,
yes I understand that the error message says that inout data_io must be a net/wire
but I thin that a logic type can get a Z value ? no?
Thanks

mrflibble · Feb 12, 2014

kaelk said:
thanks mrflibble, I tried it and it works,

Excellent.

yes I understand that the error message says that inout data_io must be a net/wire
but I thin that a logic type can get a Z value ? no?
Thanks

Quick google, because lazy: https://stackoverflow.com/questions/13282066/difference-of-systemverilog-data-types-reg-logic-bits

inout ports in verilog

kaelk

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mrflibble

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kaelk

kaelk

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mrflibble

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inout ports in verilog

kaelk

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mrflibble

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kaelk

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