LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY comp IS
PORT
(
clock_20MHz : IN STD_LOGIC;
CS : IN STD_LOGIC;
WR : IN STD_LOGIC;
RD : IN STD_LOGIC;
INT : IN STD_LOGIC;
scmpr : OUT STD_LOGIC_VECTOR(6 downto 0);
sens : OUT STD_LOGIC;
data_in : INOUT STD_LOGIC_VECTOR(7 downto 0)
);
END comp;
-- Architecture Body
ARCHITECTURE f OF comp IS
signal data : STD_LOGIC_VECTOR(7 downto 0);
BEGIN
PROCESS(clock_20MHz,CS,WR,RD,data)
BEGIN
IF (WR='1' AND RD='0' AND CS='0') THEN
data_in<=data;
ELSE
data_in<=(OTHERS=>'Z');
IF (clock_20MHz'EVENT AND clock_20MHz='1') THEN
IF (WR='0' AND RD='1' AND CS='0') THEN
data<=data_in;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS (INT)
BEGIN
IF (INT'EVENT AND INT='0') THEN
scmpr <= data (6 downto 0);
sens <= data(7);
END IF;
END PROCESS;
END f;