-- Select a register to read using appropriate read-enable signal
-- NOTE: The output buffers of the external data supplier must also be
-- driven into the Z state.
-- The synthesis tool will generate 3-state buffers.
DATABUS <= REG1_OUT when REG1_READ_EN = '1' else "ZZZZZZZZ";
DATABUS <= REG2_OUT when REG2_READ_EN = '1' else "ZZZZZZZZ";
-- You can use DATABUS directly as input.
-- The following will set DATABUS_ZERO to "true" whenever DATABUS is 0,
-- regardless of where the zero came from (e.g., it can come from REG1_OUT).
DATABUS_ZERO <= '1' when DATABUS = X"00" else '0';
-- Update registers using appropriate write-enable signal.
-- Use registers to "capture" input data.
U_REG1: process (clk)
begin
if rising_edge(clk) then
if REG1_WRITE_EN = '1' then
REG1_OUT <= DATABUS;
end if;
end if;
end process;
U_REG2: process (clk)
begin
if rising_edge(clk) then
if REG2_WRITE_EN = '1' then
REG2_OUT <= DATABUS;
end if;
end if;
end process;