inout - is used for ports that can both be an output and an input. They're called tri state buffers
if you define a port as inout, you also have to define it's behaviour.
Suppose "some_inout " is defined as an inout std_logic port in your entity.
Code:
some_inout <= x when control_signal = '1' else 'Z' ;
when "control_signal" is '1' "some_inout" functions as an output.
when "control_signal" is '0' "some_inout" functions as an input.
To understand the buffer type you have to know about a strange limitation that VHDL has...a simple "out" port cannot be read back to the design(!).
Suppose "some_out" is a port that defined as an "out" std_logic in your entity. you won't be able to read back the value of "some_out" in the same architecture:
For example, you won't be able to write:
Code:
if some_out = x then
-- do something --
end if ;
You'll have to define and use an intermediate signal like this:
Code:
some_out <= intermediate_some_out;
if intermediate_some_out = x then
-- do something --
end if ;
A buffer type is an output type that unlike a simple "out" - can be read back without problem...so you can write:
Code:
if intermediate_some_out = x then
-- do something --
end if ;
- - - Updated - - -
You can also read this:
http://vhdlguru.blogspot.co.il/2011/02/how-to-stop-using-buffer-ports-in-vhdl.html
I'll note that the use of buffer type is discoraged by many...
Myself, I'm not convinced.