Inline MOSFET in-rush current controller - not working out for me!

G'day All,

Recently I had an in-rush spec added to a design spec from my customer and as usual this was after the hardware design had been approved and manufactured.... typical. Anyway the'yr paying!

In the interim a stand alone circuit is to be used in the prototype.. However I'm having difficulties understanding why my circuit doesn't behave how I expected... clearly my understanding of MOSFETs is hindering me here...

this is what i have...

I'ts a PMOS device SUP53P06 (what i had laying around) and the load I've used simulates the actual load. The reason I've constructed it like this is because I want it inline with the current power switch.. I don't want an additional (or don't have) control signal for the gate.




In the above circuit there is no soft start at all... it looks as thought the MOSFET is hard on from the beginning. and i get a nasty surge.

If I use this (see below) more conventional circuit (such as the ones described in a number of app notes)





With the source connected to V+ and switching the load via the gate resistor I get the desired result... However i need the additional control signal to toggle the gate...

Can someone explain why my first method doesn't work like the second? And some ideas how to get a soft start system from when power is first applied?

Thanks.

I would have thought the 200nF should be across the gate-source not gate-drain if you want to slow down switch-on.

Keith

I'm hearing you Keith that was my original thought.... However I'll try and explain how it is I now understand it..

1. The gate source capacitance (or more correctly gate-sorce charge Qgs which is most affected by Cgs) effects the time it takes for the gate to charge to the Vg(th) level. Basically during this period nothing really exciting happens (to an engineer anyway - possibly a different story for the physicists among us). Adding additional capacitance between this junction only delays the time before the the gate voltage reached Vg(th).
2. When Vg gets to Vg(th) and the channel begins to conduct the gate-drain 'Miller' capacitance (or Qgd - affected mostly by Cdg) then effects the way Vg progresses. It's during this time that the engineer becomes mildly aroused as this is the period in which the device switches on and hence the period in which one wants to extend. Have a look at a gate-charge waveform - this was insightful http://www.irf.com/technical-info/appnotes/an-944.pdf

Hopefully I'm on the right track?

- - - Updated - - -

I think I may have an idea of what is going on... I'm thinking its dv/dt issue... when volts are suddenly applied to the source (10us rise time) a voltage is established across the gate resistor due to the large amount of added Cdg capacitance this allows a momentary short to the fast edge and exceeds Vg(th) and the device turns on... Gotta be it right? I've been reading paragraph 5.13.1 in the link i posted previously.

Yes, I think you have worked it out before I had time to reply.

The Miller situation is different to yours. Looking at the Miller capacitance idea, the power would be on, the transistor is off and then you try to turn the transistor on (with some resistance in the gate) and the Miller capacitance (with added capacitance) slows down the gate rise as the drain voltage moves towards the source as the transistor turns on.

Your situation is different. To start, everything is off. You have 3 capacitances - the large one on your load (and a low load resistance), the Miller capacitance (with added capacitance) and the gate-source capacitance. At switch on the source voltage rises. The voltage across the capacitors will be split in inverse proportion to their values. Where one is very much larger than the others then the small one gets all the voltage. In your case the output and Miller capacitors will stay with roughly zero voltage and the transistor will be turned on.

If you had some simulation software (try free LTSpice) you could experiment and analyse what is going on, although building it works too!

Keith

The difference between the two circuits is the initial condition. In the first circuit, the 200nF capacitor is initially discharged, as is the output capacitor. This means that when you apply input power, the gate will actually be start off at 0V (FET is fully on) until the 200nF cap starts to charge through the resistor divider. That sort of kills the soft start effect.

Now look at the second circuit. Since input power has been applied before the control signal, the 200nF cap starts off charged to Vin, and when you apply the control signal, the gate voltage will fall from 13V, which is what you want.

The operating principle of the circuit is that the 200nF cap should effectively limit the dv/dt on the output by negative feedback. However, this of course only works if the Vgs of the FET is biased near its threshold, and that won't be the case initially in your first circuit.

It should also be noted that even the second circuit is very flawed. Even with the control switch off, if you apply a fast rising edge on the input voltage, the PFET will still turn on and you'll get a surge of current to the output, since once again the 200nF cap will hold the gate at 0V initially.

Unless you're willing to make real soft start circuitry (current limits, maybe with foldback), you should probably just stick with a large gate-source capacitance. Just play around with the time constants until you get what you want.