INL & DNL simulation using Spectre Cadence

[pnanda65675]

i have this 10-bit pipeline ADC that operates at 6.75Mhz, i wanna test INL & DNL factor for my ADC, i knew it supposed to be done using transient analyses...what type of input i should give, i've differential input in to ADC. ANd how long u need run & how many hours does it takes???

 

[shpongle]

In practical cdtions, it depends on your resolution but here you can generate ideal stimuli.

A ramp (up and down) should be good to generate an histogram. Slightly overload (10 %) your converter input to be sure you cover the whole range. Slope of ramp linked to the number of samples/bin you need: accuracy proportional to 1/N where N is the average number of hits/bin. Then histogram, neglect both side codes and compute DNL, INL. It can be very long...

Very interested if someone has a better idea

 

[kytan]

You can do that with a ramp but finally when you got your chip designed it is very hard to get a good ramp output from an actual bench instrument to verify whether your theoretical result is close to the real result, so the industry uses sine wave by default since sine wave generation is most "clean" meaning no phase noise very little harmonics. You still get a histogram but more hits at the peak and trough of the sinewave than in the middle. Please refer to the IEEE std 1241 for the recommended testing and computation approach that I have just talked about. The computation is more complex as you can see from the IEEE standard document

 

[shpongle]

any idea about a method avoiding the long process of capturing output samples for histogram ?

 

[rambus_ddr]

In cadence simulation, the opamp and comparator is almost ideal(no offset and no noise at tran simulation), then the INL and DNL at the results of simulation is better than the results of chip test. How can I add this nonideal facts at cadence, and get a statistical results, and modify my design. Thanks your advice!