Puppet123
Full Member level 6
Hello,
I want to measure the INL/DNL of an ADC designed in Cadence Spectre/Virtuoso.
I understand the methodology: apply an ideal DAC at the output, apply a ramp signal, or a sine wave and get the output and generate a histogram of the output codes.
My question is: how to I generate a histogram of the output codes - that is - a plot of the code vs. the code density (how many times the code appears) in Cadence Spectre/Virtuoso ? Won't it just generate the output What should I make the output look like in Cadence Spectre/Virtuoso - what format - in order to post-process in MATLAB and get the histogram of the output codes ?
Can I use a Verilog-A block in ahdlLib ? Or is their another method ?
Does anyone have a tutorial, reference, paper or thesis that describes this methodology in Cadence Spectre/Virtuoso ?
Thank you.
I want to measure the INL/DNL of an ADC designed in Cadence Spectre/Virtuoso.
I understand the methodology: apply an ideal DAC at the output, apply a ramp signal, or a sine wave and get the output and generate a histogram of the output codes.
My question is: how to I generate a histogram of the output codes - that is - a plot of the code vs. the code density (how many times the code appears) in Cadence Spectre/Virtuoso ? Won't it just generate the output What should I make the output look like in Cadence Spectre/Virtuoso - what format - in order to post-process in MATLAB and get the histogram of the output codes ?
Can I use a Verilog-A block in ahdlLib ? Or is their another method ?
Does anyone have a tutorial, reference, paper or thesis that describes this methodology in Cadence Spectre/Virtuoso ?
Thank you.