i'm new to the DFT technique. hope anyone can help me. i've designed a
LFSR to test the 3 bit ALU. firstly, i'vr try to simulate the LFSR
using xilinx ise 9.2i, but no output signal is produced (only input
signal, which is reset and clock). i've read some books and articles,
tell that we need to initialize the LFSR by seeding with non-zero
value. how can we do this?
If you are using an SRL16 shift register primitive, you could attach an "INIT" attribute to the schematic symbol and set it to a non-zero value. That would initialize the register upon FPGA configuration. Or use XNOR feedback so the SRL16's default zero initialization works fine. However, an SRL16 doesn't provide any run-time reset input.
If you really need a reset input, you could use a general-purpose shift register with synchronous load such as an SR16RLED. Your reset input would synchronously load the initial value into the register. For asynchronous reset (usually not a good thing in FPGA), I suppose you could use something like an SR16CLED which has an asynch reset (for the reset-to-zero bits), perhaps combined with an FDCP flop (for the reset-to-one bit). Pretty messy. You could avoid the FDCP by using XNOR feedback and by resetting the register to 0. Any of these methods will consume significantly more FPGA resources than an SRL16.
Your ISE documentation include special Libraries Guides for schematic entry. They describe the various register types, and attributes such as INIT.
Most engineers find HDL much easier than schematic entry. Consider it!