initialization in verilog HDL

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preethi19

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can someone pls explain me the initial statement in verilog HDL. I mean we initialize a value within the always statement block for the variable then why do we need initialize and also it is told that it executes only once that too during simulation. wat does this mean. i mean if we use initialize in the verilog code shouldn't be executed during synthesis also why only for simulation. I'm just started with few basics pls correct me if i am wrong
 

Hello

In stimulation if you want to start analyzing the functionality with specific start value the initial block is used. Where as the always block is always depends on the behavior of the functionality.

Intialization is not synthesisable

After synthesis the functionality you have written is converted to RTL with specific choosen library and hence cannot be harwired to specific values: ex assign a=1'b0; which means the specific signal is grounded in the starting which should not be your RTL.

Hope this clears your doubt.
 

so if initial statement is used to initialize the value to analyze the functionality then why do we give input values. I mean don't we specify input values for a circuit for it to function. so then the circuit must have that value as the initial value during simulation right. why do we need initial statement then. whats the difference between input and initial statement. Sorry if i'm wrong but pls help.
 

Hi

yes you are right, as i said earlier that it is just for checking up the functionality so you can just put your prediction for the start up values. even you can use the starting input as the inputs whatever you want in the testbench that is possible only you are sending certain no. of test variable only if you are sending the random test variables than the initialization is helpful "only for stimulation". if you dont want to use initialization than you can either use reset values to start the functionality with the specific values or you can send the input whichever you desire
 

hi,
for an example
if we need to generate the clock in verilog testbench, we toggle the clock by initializing its initial value in the initial block

Code: 
initial
begin
    clock = 1'b0;
    resetn = 1'b0;
  #100
   resetn = 1'b1;
end

always #10 clock = ~clock;

if we are not initialize the initial value of clock then the negated value became unknown
 

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