initial type of std_logic_vector

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rameshrai

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hi,

when we have input port like-

Code: 
a : in std_logic_vector(7 downto 0)

what is the initial data type? i mean is it integer, unsigned or signed integer? and is it one's or two's complement.

thanks
 

Its none of the above. Its just an 8 bit connection.

- - - Updated - - -

Lets just clarify this a bit.

If the engineer who wrote the code intended it to be a signed or unsigned value, they would have declared it something like:

a : unsigned(7 downto 0);

(s)He could have been one of those people that insist on std_logic_vector for everything, in which case you'll have to read the docs or speak to them what they mean that bus to be.
 
Adding to the question, when we declare the library as IEEE.std_logic_unsigned.all or IEEE.std_logic_signed.all I believe all the data types become unsigned or signed accordingly, am I correct ?
 

verylsi said:
Adding to the question, when we declare the library as IEEE.std_logic_unsigned.all or IEEE.std_logic_signed.all I believe all the data types become unsigned or signed accordingly, am I correct ?
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Nope. A std_logic_vector is still just a collection of bits. These libraries just allow you to do arithmatic as if the std_logic_vector was an unsigned/signed. But these packages are not part of the VHDL standard, so using them does not give you IEEE compliant code (and it makes you look like you're stuck in 1992)
 

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