Information on how to interface with RAM stick included with Stratix III DSP Devel

I had posted previously on how to get my design in DSP Builder to work in Quartus II with SignalTap II Logic showing 128k output instead of 8k. I finally found a way to get the design compiled in 16k instead of 8k, however I noticed that it if I attempt to compile it at 32, 64, and 128k, the design will not compile due to a shortage of memory. The FPGA board is the Altera Stratix III DSP Development Kit. It comes with an add-on board of 1GB of RAM. Putting this on the board should get it to compile up to 128k, but after putting it on, it hasn't worked. I'm guessing the board has not recognized it or can't interface to it. Does anyone know how to verify that the board is seeing the RAM add-on and if it's not seeing it, how to interface to it?

Thanks,

Daniel

I'm a Xilinx man myself... but you probably need to interface to the DDR2. You can't just plug it in and go! Interfacing to DDR2 is not trivial. I would investigate some kind of Altera documentation on it. Xilinx has Memory Interface Generator which generates the interface and controller between FPGA and DDR. I'd think Altera has something similar. Even with MIG, it's not trivial.