Re: four corner sta
Four corner checking is the combination of slow or fast corner for P channel and slow or fast corner for N channel.. At least that's the definition our circuit design team had long time ago.
There are cases that SF corner(S: P channel, F: N channel) can be more prone to hold viols than FF.
For example, consider the path that is made with the series of transmission gates. Clock tree is made with buffers or inverters, where both of P channels and N channels are equally exercised, so that SF corner gives you larger clock skew than FF corner. Now suppose the data path has many transmission gates connected serially. As you know, P channel of transmission gate doesn't contribute to the delay much since the major role of P channels in the transmission gates is just pulling up the node voltage beyond the threshold of N channel. So, the delay of transmission gates heavily depends on N channels where the fast corner is used for.
In this scenario, you have larger clock skews, but not much change on data path delay, comparing to FF corner. What does it mean ? Apprarently, it means SF corner is more prone to the hold violation than FF.