Inferring design elements in Verilog

[Giox]

Hello everybody,
I have some problem with Xilinx libraries. In fact I'm programming in Verilog HDL and I would like to use the specific design elements provided by xilinx. However in the Libraries Guide many times the inferred code is not shown. Do you know what is the pdf document that provide the code?
Thanks a lot to everybody
Giovanni

 

[echo47]

Can you give us a specific example? The info may not exist. Why do you need it? That may help us answer your question.

 

[dBUGGER]

Hello everybody,
I have some problem with Xilinx libraries. In fact I'm programming in Verilog HDL and I would like to use the specific design elements provided by xilinx. However in the Libraries Guide many times the inferred code is not shown. Do you know what is the pdf document that provide the code?
Thanks a lot to everybody
Giovanni

Hi giovanni...
I f you are using XILINX ISE software then you can use the templates provided by Xilinx itself. You can open the templates by going to EDIT menu and clicking on language templates. Here you will get the code for inferring the xilinx primitives and other components in both Verilog and VHDL. Hope this helps.

Best Regards,

 

[Giox]

Thanks to both echo47 and dBUGGER, in fact I'm interested in the ADSU block, but I saw that there is no template provided. However thanks a lot (I didn't know until today the use of templates in ISE 7.1).