Not actually clear what you tried to achieve. A constant value can be altered e.g. in a generate loop but not in regular concurrent or sequential code. That's why we call it a constant.
Oh, I didn't see at first view what you meaned with this funny "REG"&i expression. There's no VHDL syntax to generate dynamical object names. By the way, do you know a hardware description or programming language that has it?
Please get a VHDL text book and take a look at arrays. There are also arrays of constants.