Increasing Yield of a chip.

Hi,

Can someone pen down few points for increasing yield of a chip.

Thanks,
Kashfi Israr

HI ,


..> using multi cut vias to increse yield
..> there should not be a electro migration problem


Regards
chiranjeevi

3. Make sure that you take into account process variation in your design. You can do this either by making a circuit that can tolerate those variations or by designing a circuit with minimal variation (for example, using dummy transistors and common centroid layout in differential pairs)

Thanks alifalif and chiranjeevinaidu for your answers.
Still " using multi cut vias to increse yield " is not clear to me ....can you please explain this a bit in detail.

thanks in advance
Kashfi Israr

If contact chain or via chain yield is a significant loss-point,
using duplicate vias (pair instead of single) can drive down
the loss (also, if the vias are a big issue, can improve the
reliability). But you will eat routing density big time, and
depending on the process via-yield may be hurt more by
filling than by printing and close-packed via beds can have
worse per-via yield probability than isolated or routing-pitch-
spaced ones.

To know what improves yield, you'd like the foundry to
give you the top ten detractors' defect probability, and
then you can figure, for each, feature-count*loss-fraction,
roll that up in a spreadsheet and then you will at least
have a proper set of targets / priorities.

Realize, too, that yield limiters for digital "stuff" in a
digital flow may give you little insight to parametric-limited
yield in something more analog-y that tries to use the
same flow, but devices which aren't controlled for fine
tolerance (like, good luck with the poly resistor sheets
and tempco, hence your bandgap).

Following the DFM rules while doing layout.
Following the EM rules.


The above conditions will definetly increase the Yield of the chip.

HI Kashfi Israr

I have shared below points it's my experienced ....
case1:using default cut vias probability of chips failure is exits.why because between two layers connect with single via .so via is not connected properly,so chip is malfunctioning.......

case2: using multi cut vias probability of chips failure in not exits .why because connectivity of between two layers connect with multi vias (parallel vias resistance also less ,it's help timing as well as DFM checks)


Regards
chiranjeevi

Multiple vias (best case) yield as (1-d)^N. If your yield is 99%
(d=1%) for one then it's 99.99% for two. But you can't assume
that two proximate vias yield the same as two individual, wider
spaced ones - lithography differs when geometry differs.

EM rules do not affect probe or packaged test yields except
when there is a really, really gross violation. Otherwise this is
a product reliability (failure in the field) problem, not yield per
se.