increasing gain in differential amp

[jutek]

hello

probably i'm doing wrong simulation cause the differential gain of differential amplifier increases with frequency

did you have similar problem?

 

[mince]

You are probably doing simulations wrong. If you're doing AC analysis, apply inputs of +0.5 and -0.5. If you are applying 0.5 to both inputs, then you're simulating the common-mode gain which should increase with frequency in most cases.

 

[jutek]

transient analysis looks good, so to simulate ac properly i shuld have negative inpyt grounded and positive with low ac magnitude?

can you check the circuit please?

Vdd vdd 0 DC=3.3

Vinp inp inn SIN(0.8 10m 10k) AC=0.1
Vinn inn 0 DC=0

*
Vt vt 0 DC=2.2

M1 out1 inp P vdd CMOSP W=80u L=1u
M2 out2 inn P vdd CMOSP W=80u L=1u
M3 out1 out1 0 0 CMOSN W=17u L=1u
M4 out2 out2 0 0 CMOSN W=17u L=1u

M5 P vt vdd vdd CMOSP W=60u L=1u

 

[mince]

For your inputs, do something like this:

Vinp AC=0.5
Vinn AC=-0.5

Plot the AC output, this will be your AC differential mode gain.

Also your inputs need to have a DC bias since your lower rail is ground. Let the DC value be Vdd/2 for now. It can be optimized later. If your inputs have a DC of 0 right now, transistors will not be working properly and won't act correctly as an amplifier.

 

[jutek]

are you sure?

when i use dc bias equal 1.5V transistors M2,M4 are cutoff

and when i use ac=0.5 and ac=-0.5 (?) the results are very strange

i simulate everything using hspice

 

[mince]

Did you do this?

Vinp inp 0 DC=1.5 AC=0.5
Vinn inn 0 DC=1.5 AC=-0.5

And then for your transient add this line:

Vtran inp inn SIN(0.8 10m 10k)


There's no way it will work with your input DC=0 due to your common mode input range. Your common mode range is:

-Vss+Vdsat3+Vtn-Vtp < Vcmdc < Vdd - Vdsat5 - Vdsat1 - Vtp

So for example, if your Vdsat= 200mV for each transistor, Vtn = 0.7, Vtp = 0.9, then your input range will be:

0+.2+.7-.9 < Vcmdc < 3.3 - .2 -.2 - .9
=
0 < VCMR < 2

Theoretically it will work at 0 V input, but it will be right on the edge of saturation/triode, so this is not a good bias point for this example.

 

[jutek]

i don't know what's happening but ac analysis doesn't work

i did as you wrote. maybe i do the plotting wrong? i use VDB(out2,out1) or V(out2,out1)/Vinp and V(out2,out1) but each case isn't 1 or 0db as expected.

I also did the transfer function analysis to make sure that W/L ratios gives me unity gain and it does.

 

[mince]

Can you post your whole netlist?

 

[jutek]

sure

*differential output

.OPTIONS LIST POST NODE NOMOD

.LIB "tsmc_025um_model" CMOS_MODELS

******sources*****

Vdd vdd 0 DC=3.3

Vinp inp inn DC=0 AC=0.1 SIN(0 10m 10k)
*Vinn inn 0 DC=1.5 AC=-0.1
Vcm inn 0 DC=1.5

Vt vt 0 DC=2.2

M1 out1 inp P vdd CMOSP W=80u L=1u
M2 out2 inn P vdd CMOSP W=80u L=1u
M3 out1 out1 0 0 CMOSN W=17u L=1u
M4 out2 out2 0 0 CMOSN W=17u L=1u

M5 P vt vdd vdd CMOSP W=30u L=1u


*******analyses****
.OP
*.DC Vinp 0 3.3 0.05
.TRAN 5US 200US
.AC DEC 10 10 100MEG
.TF V(out2,out1) Vinp

*******plots******
.PLOT AC diff=PAR(`V(out2,out1)/V(inp)`)
.PLOT AC Vdb(out2,out1)
.PLOT AC V(out2,out1)
.PRINT DC V(out2,out1)
.PRINT DC I(M1) I(M2)
.PRINT TRAN V(out1,out2)


.end

 

[mince]

your AC input sources need to be from the input to ground, not from input to input.

Change:
Vinp inp inn DC=0 AC=0.1 SIN(0 10m 10k)
Vinn inn 0 DC=1.5 AC=-0.1
Vcm inn 0 DC=1.5

to

Vinp inp inn DC=0 SIN(0 10m 10k)
Vinn inn 0 DC=1.5 AC=-0.1
Vcm inn 0 DC=1.5 AC=0.1

 

[jutek]

what you wrote also doesn't work

i have used LTSPICE with this netlist and it works

M1 N002 N004 N003 N003 cmosp l=1u w=50u
M2 out1 N001 N002 N003 cmosp l=1u w=600u
M3 out2 N005 N002 N003 cmosp l=1u w=600u
M4 out1 out1 0 0 cmosn l=0.5u w=1u
M5 out2 out2 0 0 cmosn l=0.5u w=1u
V1 N004 0 1.8
V2 N003 0 3.3
V3 N001 0 1.5 AC 0.1 0
V4 N005 0 1.5 AC 0.1 180
.ac dec 10 1 10meg
.end

so i wrote in the hspice

Vinp inp 0 DC=1.5 AC=0.1V,0
Vinn inn 0 DC=1.5 AC=0.1V,180

but it still doesn't work. i have 0 at the differential output. at single outputs, the response increases with frequency. i don't understand the difference between ltspice and hspice

 

[flamingo]

First, you should assure that every devices in your circuit working in proper condition, USE DC and OP to debug your ckt. after this, do ac analysis, also ensure devices' working conditions are the same as in DC analysis. Simulator or commands syntax are not the chief criminal, the KEY is your understanding into the ckt, good luck!

 

[jutek]

i assured the devices work in saturation region in OP analysis but working conditions changed in AC and surely this caused inproper working. how to polarize inputs during AC simulation to have DC offset. this way i did doesn't work.

regards