increase or decrease a reg

Code Verilog - [expand]
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module key_speed
    #(parameter speedDefault = 2, speedMax=4, speedMin=0)
    (reset, keyUp, keyDown, speed, reset_reg_eight);
input reset, keyUp, keyDown;
output reset_reg_eight;
output reg [2:0] speed;
 
 
always @(negedge keyUp or negedge keyDown or negedge reset)
begin
if (~reset)
    speed = speedDefault;
    else 
    begin
        if (keyDown==0)
        begin
            if (speed!=speedMin)
                speed--;
            else speed = speed;
        end
        else if (keyUp==0)
        begin
            if (speed!=speedMax)
                speed++;
            else speed = speed;
        end
    end
 
end
 
assign reset_reg_eight = (keyUp&keyDown);
    
endmodule