2.6.4 PLL IN INTOSC MODES
The 4x frequency multiplier can be used with the
internal oscillator block to produce faster device clock
speeds than are normally possible with an internal
oscillator. When enabled, the PLL produces a clock
speed of up to 32 MHz.
Unlike HSPLL mode, the PLL is controlled through
software. The control bit, PLLEN (OSCTUNE<6>), is
used to enable or disable its operation.
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
source (FOSC3:FOSC0 = 1001 or 1000). Additionally,
the PLL will only function when the selected output frequency
is either 4 MHz or 8 MHz (OSCCON<6:4> = 111
or 110). If both of these conditions are not met, the PLL
is disabled.
The PLLEN control bit is only functional in those internal
oscillator modes where the PLL is available. In all
other modes, it is forced to ‘0’ and is effectively
unavailable.
#pragma config OSC = INTIO67
OSCCON = 0b01110010; //select 8 MHz clock
Can someone plzzzzzzzzz tell me how I can increase 8 to 32 MHz!!
OSCTUNE = 0b01000000;
Also if and when I do manage to get my Fosc to 32 , would my instruction clock be Fosc/4 = 32/4 = 8Mhz?
Code:/* Clock Setup*/ OSCCON = 0b01110010; //select 8 MHz clock OSCTUNE = 0b01001111;
OSCTUNE = 0b01000000;
OSCTUNE = 0b01001111;
OSCTUNE |= 0b01000000;
Yup that gives me 2 MHz at RA6 .
I was fiddling around with these bits to get MAX frequency out.
OSCTUNE (BIT 4:BIT0)
bit 4-0 TUN4:TUN0: Frequency Tuning bits
01111 = Maximum frequency
• •
• •
00001
00000 = Center frequency. Oscillator module is running at the calibrated frequency.
11111
• •
• •
10000 = Minimum frequency
By the way, whats " |= " this?
A = A | B;
A |= B;
" FOSC3:FOSC0 should be 1001 or 1000 " for PLL to work.....Its only set in the configuration bits I suppose [OSC= INTIO7 or INTIO67]?
" FOSC3:FOSC0 should be 1001 or 1000 " for PLL to work.....Its only set in the configuration bits I suppose [OSC= INTIO7 or INTIO67]?
TABLE 23-1: CONFIGURATION BITS AND DEVICE IDs
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
300001h CONFIG1H IESO FCMEN — — FOSC3 FOSC2 FOSC1 FOSC0 00-- 0111
300002h CONFIG2L — — — BORV1 BORV0 BOREN1 BOREN0 PWRTEN ---1 1111
I see , then why don't I get 32Mhz with this?
/* Clock Setup*/
OSCCON = 0b01110010; //select 8 MHz clock
OSCTUNE |= 0b01000000;
The PLL is available when the device is configured to
use the internal oscillator block as its primary clock
2.7 Clock Sources and Oscillator Switching
Like previous PIC18 devices, the PIC18F2525/2620/
4525/4620 family includes a feature that allows the
device clock source to be switched from the main
oscillator to an alternate, low-frequency clock source.
PIC18F2525/2620/4525/4620 devices offer two alternate
clock sources. When an alternate clock source is enabled,
the various power-managed operating modes are
available.
Essentially, there are three clock sources for these
devices:
• Primary oscillators
• Secondary oscillators
• Internal oscillator block
The primary oscillators include the External Crystal
and Resonator modes, the External RC modes, the
External Clock modes and the internal oscillator block.
The particular mode is defined by the FOSC3:FOSC0
Configuration bits. The details of these modes are
covered earlier in this chapter.
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