Increase length and Vth decrease

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twonsr

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Hi All:

If mos length increases and Vth will decrease.

Why ?

Thank you.
 

twolevel2002 said:
Hi All:

If mos length increases and Vth will decrease.

Why ?

Thank you.

DIBL effect.

Added after 1 minutes:

DIBL: Drain Induced Barrier Lowering
 

In MOS Length Increased Vth decrease ????.. Think it is as the length decreases as the S/D come closer... There would DIBL effect... and also due to charge sharing.. The Vt decreases...
 

twolevel2002 said:
Hi All:

If mos length increases and Vth will decrease.

Why ?

Thank you.

Actually Vth for bigger length is the reference Vth. You should ask "If mos length decrease, why the Vth increase"...
This happen because of the Reverse Short Channel Effect(RSCE)...
 


What is Reverse Short channel effect,,, could you please explain.. i want to know more... how does Vt increase in length decrease ??
 

I am not sure about DIBL, but you can get any Vt if you have certain doping profile. However, it may not work as FET in certain or many areas in DC Characteristics. It depends.

Usually, increase in L, decrease in λ.

Srivats
 

leelamadhav said:
What is Reverse Short channel effect,,, could you please explain.. i want to know more... how does Vt increase in length decrease ??

Nowadays we put punchthrough implant near source and drain to avoid the punchthrough. As the length decrease, the seperation of these 2 implants become smaller and eventually overlap each other. We know that this implant is the opposite doping type of the sorce and drain..... so, when this happen, as the L decrease, Vth will increase first to form hump before it follow normal trend.... that is what we call reverse short channel effect.....

Added after 6 minutes:

leelamadhav said:
In MOS Length Increased Vth decrease ????.. Think it is as the length decreases as the S/D come closer... There would DIBL effect... and also due to charge sharing.. The Vt decreases...
Vth also affected by DIBL, but this effect happen because we have high drain voltage..... the smaller the L, the bigger the effect- provided we have high drain voltage......
 

Generally Vth increases as gate length decrease. When gate length decreases further (0.1um or lower), Vth begins to decrease.
First increase is due to the reduction of controllable gate area. The gate-source(drain) overlap begin to occupy a large portion in gate capacitance. In some process space decrease between source and drain -side HALO implantation (P+ implantation) also increase Vth. But when in operation, Vth may decrease due to DIBL effect.
Second decrease has some causes. One is that electrical field from poly gate side wall begin to has effect on channel inversion. This effect is not influenced by gate length shrink. It only plays an improtant role when gate length become very small. Another cause may be that as source and drain extension diffusions approach more closely, almost all holes in the channel are depleted.

If I am not correct, please point out.

Thanks
 


In razavi's book, there is a sentence saying that vth decreases as L decreases...
but i think your opinion looks reasonable, can you give some examples of actual processes? thanks very much!
 


That is the general behaviour of the Vt when we decrease the length.... the reason is simple, as the length decrease, the amount of the voltage that needed to invert the channel is less because the channel area is reduced. That is why we will see Vt will decrease as L decrease. But for process 0.18 and below, the punctrough implant will overlap... As I said, this situation will make Vth increase first before it follow normal trend.... the reason is that, since the punchthrough impalnt is p-type for NMOS, the gate need to overcome this charge before it get inverted..... I don't have specific example for the process, but I think you serach it in google.... look for RSCE.....
 

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