[SOLVED] incorrect output VCM opampMacro simulation on Cadence

[melkord]

How to determined the output VCM when using opampMacro on Cadence?
My simulation produces incorrect output VCM i.e., out of 0-vdd range.
Changing the value of Vref does not solve the problem.

There is the similar discussion here but it is kinda old and the pictures are not there anymore.

 

[KlausST]

Hi,

My simulation produces incorrect output VCM i.e., out of 0-vdd range.

... maybe you tell us what you expect, instead?

What is "Output VCM"? Output common mode? Since there is only one ouput: "Common" to what? To supply rails?

The picture is of low quality, I can´t read texts.


Klaus

 

[melkord]

Hi,

... maybe you tell us what you expect, instead?

What is "Output VCM"? Output common mode? Since there is only one ouput: "Common" to what? To supply rails?

The picture is of low quality, I can´t read texts.


Klaus

hmm...I did not use the correct terms.
well I expected I could control the DC voltage at the output node to any value within 0-vdd range.

I updated the picture.

 

[KlausST]

Hi,

Output:
on OPAMPs the output is limited to the supply rails. Thus you theoretically can get 0V ... VDD.

Input:
Many OPAMPS also have a common mode input voltage range much smaller than 0V ... VDD.
--> what´s the common input voltage range?

Circuit:
Since it is an inverting circuit ... and the output voltage can only be positive ... this means the circuit can handle negative inputs only.
Positve input will cause the output to clamp close at the negative limit = 0V.
Negative input voltages may produce positive output.

But since the OPAMP "clamps" it comes out of regulation. The input stage may saturate, the ouput stage surely does.
Now "coming out of saturated state" may take some time on a real OPAMP. Maybe more than one halfwave of your 100kHz input frequency.
Thus in worst case you won´t see any useful output.

****
So "My simulation produces incorrect output VCM i.e., out of 0-vdd range." maybe is not correct.
True is: The simulation does not produce the signal you expected. ;-)

Klaus

 

[melkord]

Hi,

Output:
on OPAMPs the output is limited to the supply rails. Thus you theoretically can get 0V ... VDD.

Input:
Many OPAMPS also have a common mode input voltage range much smaller than 0V ... VDD.
--> what´s the common input voltage range?

Circuit:
Since it is an inverting circuit ... and the output voltage can only be positive ... this means the circuit can handle negative inputs only.
Positve input will cause the output to clamp close at the negative limit = 0V.
Negative input voltages may produce positive output.

But since the OPAMP "clamps" it comes out of regulation. The input stage may saturate, the ouput stage surely does.
Now "coming out of saturated state" may take some time on a real OPAMP. Maybe more than one halfwave of your 100kHz input frequency.
Thus in worst case you won´t see any useful output.

****
So "My simulation produces incorrect output VCM i.e., out of 0-vdd range." maybe is not correct.
True is: The simulation does not produce the signal you expected. ;-)

Klaus

Thank you.
I am checking this macro to use it as an ideal reference.
I expected I can make a quick check without creating the test bench etc.
So, I have not checked the input common mode range.

The input source in the picture has 900mV DC.

I remember I could simulate similar circuit in a simpler simulator.
Now I do not know why I could get the expected result then.

In this simulation, still the output DC voltage is out of 0-vdd range.

 

[Dominik Przyborowski]

Your opamp non inverting input is on ground, inverting on 900m and gain is -10. And you are wonder why output is at - 9V.

Really suspicious...

 

[melkord]

Thank you all.
I did not know what I was thinking.
I was expecting only the amplitude of the sine wave which got amplified.
It is clear now...at least for this circuit.