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Include file into a verilog-A code

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hosseineslahi7

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Hi,
I am trying to call or include some files into a specific verilog-A code. Each file encompasses a set of instructions. I used 'include (filename.include) in my code but this code cannot be compiled in AWR simulator. Could you please tell me how a file (verilog-A code) cqn be included in another file in order for new file to be compiled?

yours sincerely
Hossein
 

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