In UART Design , sending stop bit

Status
Not open for further replies.
K

kbkdec15

Junior Member level 1
Joined
May 27, 2013
Messages
18
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Visit site
Activity points
1,397
Hi every one ,

i am trying to design UART ( complex one )

the sout (transmit line) is high by default and the stop bit of frame also high . how can we recognize the stop bit ?

if the sout is high for both stop bit and default then how to send 1.5 bit using counter logic.
 

With the baud rate, you count the number of bit, then you know, that's the end.
 

After detecting start_bit wait 1.5 uart_clk
now you can sample the first bit. + 7xuart_clk you're on the last bit.
+ 1 uart_clk you're on stop_bit.
If the bit=1 - legal byte
you can start waiting for start_bit
sys_clk should be at least uart_clk/16
 

hi meir ,

please tell me if uart_clk is baud_rate_clk then we have to count the uart_clk with respect to sys_clk. what is legal byte in above algorithm .


thanks
kbkdec15

- - - Updated - - -

thanks rca, how to count .5 bit with respect to baud rate. tell we have to send bits at level of baud_rate_clk or at edge of baud_rate_clk .
 

yes by uart_clk I mean the uart baud rate. Usually the uart baud rate is derived from sys clk.
The uart bit is transmitted on edge of uart_clk and should be stable for 1 uart_clk
uart rx is sampled around the middle.
If stop_bit is not detected 10 bits after start_bit bit the previous sampled 8 bits are discarded
 
Last edited:

thanks meir. my uart_clk 50% duty cycle.

one uart_clk cycle = (16*buadrate ) sys_clk cycles.

here 1.5 stop means

one uart_clk cylce (i.e 16 sys_clk ) + half uart_clk cycle ( 8 sys_clk) = 24 sys_clks .

sending serial data with respect to baud rate, that is synchronous with posedge of sys_clk.

i am uable to count 24 sys_clk cycles. the counter is leading wrong stop bit . (this at transmitter side).

thanks
kbkdec15
 

The method I described was for detecting uart i.e uart_rx.
At the "beginning of the world" when waiting for start bit you have to sample every sys_clk i.e. at least 1/16 of uart_clk.
When transmitting uart byte you transmit every 16 *sys_clk. it is the receivers responsibility to sync on your start_bit
 
hi meic ,

thanks

how can we recognize parity bit and stop bit on rx line.

we will receive stream of bits after start bit on rx line , and we do not know the payload size and , parity is enable or not and how many of stop bit are there?

regards
kbkdec15
 

Hi,
Receiver side there is no such intelligence provided to check payload size of which is the parity bit, as all data coming on signle line.
On both transmit and receive side we have to make sure that all the settings like no. of stop bit, payload, parity enabled has to be same.... This thing is assumed by receiver logic...and according receiver logic look for the resepctive bits...Ex. If parity is enabled on both sides then logic will check for parity....otherwise not...similarly for stop bits and paylaods.
Stop bit 1 or 1.5 basically come in picture for continuous data transfer. In such case Ex: atfer 1.5 stop bit immediately next start bit will come on Sout.
Hope you got some idea.
 
IF you found it helpful, press Helped me button............
Thanks
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…