In 2-D memory array, how to force a specific address to 8'hFF?

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Hi,

In Verilog, I'd like to set the address 0 of the memory array below to 8'hFF.

[ memory model ]
reg [7:0] MemoryBlock [0:EEP_END_ADDR];

[ testbench ]
force tb.u_memory_model.MemoryBlock[0] = 8'hFF;

But I had an errror.
'Illegal use of a bit-select, part-select, member-select or mda element'

Let me know a good way...

Thanks.
 

if my understanding is correct, it'll need one more construct to be added.

force tb.u_memory_model.MemoryBlock[0][x] = 8'hFF;

x can be anything based on the width/column/pointer that needs to be addressed.
 

Hi,

The result is,

force tb.u_memory_model.MemoryBlock[0][7:0] = 8'hFF; -> error
force tb.u_memory_model.MemoryBlock[0][0] = 1'b1; -> error

Sorry, but give me an another way...

Thanks.
 

Hi,

In general,

initial begin
force MemoryBlock[addr] = initial value;
end
 

Hi,

Sorry, but it still has an error as shown below.
Please correct me if I have something missing.


Thanks.

[ RTL code ]
initial begin
force tb.u_memory_model.MemoryBlock[0] = 8'hFF;
end

[ Simulation ]
force tb.u_i2c_slave_model.MemoryBlock[0] = 8'hFF;
|
ncelab: *E,ASNUSE : Illegal use of a bit-select, part-select, member-select or mda element [9.3.1(IEEE)].
 

Hi,

Your answer is exactly right in case of initializing at the beginning.
But, at a specific time of simulation, I want to set the address 0 to 8'hFF in my testbench.
In that case, 'force' could be the right way.

Thanks.
 

HI,
I am having th same issue which forcing 2D array element of a memory. I am using ncverilog

"force tb.u_memory_model.MemoryBlock[0][0] = 1'b1;".

Please help me if you have already resolved.

Thanks
 

From standart:
In contrast, the left-hand side of the assignment in the force statement can be a variable reference or a net
reference. It can be a concatenation of any of the above. Bit-selects and part-selects of vector variables are
not allowed.
 

I tried to model similar situation in Xilinx ISim... and it works fine!
So ISim is not strictly following IEEE standart?
 

It is strange. I use cadence ius, it refers to 9.3.1(IEEE).
 

You cant straight away force the memory content. Instead you can do simulator commad to dump the memory content. If you use NCSIM "memory -dump ..." is the option, similar to your tool identify the command, once you dumped the txt file modify the memory content and reload again to the memory with the modified value NCSIM command is "memory -load ....." This will work your purpose. Any memory content modification is possible only through front-door access, the memory dump and load option is back-door load access.

-paulki
 

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