ali kotb
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hello All ,
I am trying to prove the matlab code via veriloga opamp model with ideal switches and capacitors on cadence,
to prove the STF, NTF, OSR according to Schreier ,I need to do an impulse response check on my ADC, this simply means removing the Quantizer from the loop and with a veriloga model I can generate a sequence of impulse response with pulse width =clk period of Quantizer
My Question:
is it possible to perform such check on ADC where input is DC (bandgap o/p) yet changes many times according to some important switching activity within the clk period of Quantizer ?
I am trying to prove the matlab code via veriloga opamp model with ideal switches and capacitors on cadence,
to prove the STF, NTF, OSR according to Schreier ,I need to do an impulse response check on my ADC, this simply means removing the Quantizer from the loop and with a veriloga model I can generate a sequence of impulse response with pulse width =clk period of Quantizer
My Question:
is it possible to perform such check on ADC where input is DC (bandgap o/p) yet changes many times according to some important switching activity within the clk period of Quantizer ?