That's wrong! You should connect substrate to VDD. Change it and simulate again. By the way do you simulate PSRR by AC or transient analysis?
And what is your VDD range?
you DO not need connect the gate of M1&M3 to node X, just get rid of it and connected to the output of OP. And what about the gate of M2&M4 ? just refer to Razavi's book to find out how to bias the cascode stage.
I think this structure is not good, the error amplifier output connect with the cascode PMOS gate, not thegate of M1 and M2 , then the gain will be very low. so i think that the error amplifier output connect with the gate of M1 and the M1 gate can't connect with the drain of M2.