IMPORTANT VERILOG CODING PROBLEM

[choonlle]

Case A:
always @(ctrl or dataIn0 or dataIn1)
dataOut <= (ctrl) ? dataIn1 : dataIn0;

Case B:
always @(ctrl or dataIn0 or dataIn1)
dataOut = (ctrl) ? dataIn1 : dataIn0;

Which case is correct? WHY?

 

[ls000rhb]

Case A: is correct!

 

[sheik_vb]

No Case B is correct. Because combinational logic.

 

[sachingorkhe]

case B is correct as it is combinational assignment. bcoz for combinational circuit use blocking assignments. h/w in both the cases will be the same.. it only affects simulation

Sachin

 

[choonlle]

I make final conclusion :

A is correct !


Finally, i get this answer from Verilog Coding & Synthesis Book.

 

[sheik_vb]

Can you please upload that book