Importance of Design Rule Check

So I've been trusted with designing a PCB for a large company project. I've solved most of the original issues I've had with it, set out my own design rules alongside defaults and auto routed it (because I think an algorithmic router will do better than me), I could be treading on coals with that statement but hopefully some people get me.
Everything seems ok I've double checked each minute area of the PCB and I'm happy to create the files for manufacturing. But when I run a DRC which I've never really done in the past because I always used to cut stuff out at uni which doesn't really matter if we screw it up, I get about 74 rule violations.
-70 Minimum Solder Mask Silver violations
-3 Silk to Silk
-1 Silk to Solder.
Because I'm still a beginner in this field I don't know how important these violations are?
And can someone tell me if a manufacturer will still fabricate a PCB if it doesn't 100% pass the DRC?

Things to note:
I'm using Altium Designer 14.3
I had to create my own footprints for the design.
Can someone also clarify if my board has two layers of copper that I've routed on, am I talking about a two layer board? Because theres obviously more than two layers to the board. Sorry if this is all quite elementary.

You should know that the biggest defect in manufacturing is solder usually from bad designs not process controls or materials. So use rules that fit your manufacturing house process rules and ask them to confirm. DRC is to improve assembly solder yields and board fabrication yields among other things like performance and balanced copper for low warp.

First of all: setting up an autorouter to produce quality results requires so much experience and efforts that in almost all cases the results compare rather poorly to a manually routed board. It can be useful to quickly lay out non critical tracks on the board, but most experienced PCB designers will tell you to take stuff in your own hands. Autorouters tend to ignore harnesses and buses, and thus create random patterns with excessive vias (thus increasing trace resistance).

That said, Altium allows you to define almost anything PCB related as a PCB design rule. Some rules are automatically generated with every new PCB, but not all of them are critical. In your case for example:
- The minimum solder mask sliver defines the minimal width of solder mask strips between the pads of ICs. Smaller solder mask strips simply can't be fabricated, which means that there won't be any solder mask between the affected points. The default is 10 mil however, which means that most IPC compliant SMD footprints like QFN and TSSOP will always violate this rule. If you apply an appropriate amount of solder paste, then ICs can also be soldered without a solder mask between pads, so don't worry too much about this. This rule is particularly useful to set between high voltage tracks because having no solder mask might allow these tracks to arc over.
- Silk to Silk: no idea why this rule was even invented, it tells you when overlay objects like component outlines and designators are too close to each other. It has a purely aesthetic purpose, and won't affect the functionality of your PCB in any way.
- Silk to Solder: allows you to set a minimal distance between overlay objects and solder mask edges or exposed copper. It's useful to set this rule to a small value for the entire board, like 6 mil for example, to keep overlay artwork and text far away from exposed pads. This allows for some variations in the screen printing process, while protecting your copper pads from getting covered in paint and thus cause trouble during soldering.

If your board has two layers (with tracks on the red layer = component side and on the blue layer = solder side) then you definitely have a two layer (double sided) board. By "layers" PCB designers mostly refer to the electrical layers of a board, not the overlays, solder masks, solder paste, keep out, anything mechanical, ... So a single sided board is a board with one copper layer (either top or bottom), a double sided board has a copper layer on both top and bottom, a 4 layer board has a top and bottom layer plus 2 internal layers, etc.

Thanks for both your responses that's helped me a lot. The facility we're sending it to, I think takes my PCB design and generates the Gerber files themselves but I'm not at that stage of sending it through yet so I'm not too worried at this point I'll have to do a bit more research into gerbers and drill files etc. The switches in my design are in fact SMD so its interesting you mentioned that because thats most likely where the violations came from.
I'll set the silk to solder to something and see what that does.
On a side note, I now get what the solder mask layer is I didn't really get it before, I've only every dealt with single sided boards where the copper is exposed.
So am I right in thinking the Top Overlay and bottom overlay in Altium is the Silkscreens?
I'm just not sure what is the mechanical layer and keep-out layer?

You ought to know orientation and choice of solder technology makes a difference on IPC pad selection. for 2x sided boards.

You also ought to have a good foundation in EMC design and stripline design for ns speed signals or high current slew rate.

Since power and ground is left to your imagination on the schematic, discuss the strategy of EMC design.

People forget about testability early in the design stage. But DFT has to be done before layout.

You have a lot to learn

Design rules are there to keep us from making mistakes that cause problems later on.

Silk to copper is there so that we do not put silkscreen\legend\ident on the exposed pads - this is because it then prevents soldering. The manufacturer may run a check & remove any legend that is 5thou from the pad edge.

Hi again guys,

Thanks for all your help its helped me a lot with my design. I contacted the manufacturer to ask what they prefer in terms of routing etc and made a few tweaks which have brought my design rule violations from 74 to 4 which is great. I'm keep continually learning and being able to ask you guys is pretty handy indeed.

In terms of the above @SunnySkyGuy, a lot of what you mentioned I had no idea what it was so I had to do my research first but I get part of what you were saying. Before I began the design my boss did briefly go over ground planes and loop areas etc, that was all part of my design to cancel noise, CMR etc. But I no where near advanced enough to address a lot of what you mentioned.

I appreciate all your advice!

Some basic PCB related links FYI:grin:

When a design fails , who will fix it? When it works but still fails with yield issues, who will fix it? When the repair time is too high, who will fix it? When the design is poor because the repair techs do not have an functional test box with a test header to interrogate the critical circuit response, who will fix it?

This is why a design engineer must learn how to do Design for Test and add this design to the schematic, and layout details.
Ask. If tiny volume ok. If large volume and critical to performance, include self test ports, test header buffered signals or functional test internal. Will the cost of failure exceed the cost or repairs and cost of design ( DFT/DFM/DFC)

This is a gross over-simplification, but gives you a clue.

Most important thing to remember is that DFT is not an afterthought or a serial process. It must be taken seriously from the starting gate in any functional design process.