import verilog & VHDL mixed-language design with Debussy

[foster_cn]

import vhdlpackage to verilog

Hi, Does any one know how to import verilog & VHDL mixed-language design with Debussy? How to edit *.f design list file?
my debussy version is 5.2v9, I think it should support this feature.
Thanks ahead!

 

[foster_cn]

debussy 支持 verilog 和vhdl

does anyone can help? thanks

 

[adanshen]

import verilog

debussy can support pure analog and
pure digital, so I guess it can support
the kind of mixed design

 

[roger]

vericom vhdl

you can not use .f file to load the mixed design
you have to compile them to debussy data base
vericom verilog_file
vhdlcom vhdl_files

import the design from library! 8)