I am implementing a cache memory in FPGA.
for that i need a memory of 16 bytes wide and 256 entries.
I am implementing using VHDL.
the problem is I want to download in FPGA.
Is there any way to make effective utilization of area in FPGA in this application
Yaa thanks I am using a virtex II block Ram .but still I want to know whether a super scalar fetch engine can be downloaded into FPGA or not .memory size is
two 144 by 128 memories ,sixteeen 16 by 64 memories and a 164 by 64 memory