Implementation of Clock Gating for Two clock Signals !

[msdarvishi]

Hello everybody,

I am wondering to know whether is possible to to change the clock frequency of a circuit dynamically (e.g. switching from CLK1 to CLK2) by the benefit of clock gating technique without stopping the circuit and while the circuit is running? As you know, when there are two clock signals (CLK1 and CLK2) we will have 4 transitions and we are extremely restricted not to use clock gating at those transition times ! Does anybody know how to deal with it?

Thank and Regards,

 

[code_slave]

Might be a basis for research

https://www.xilinx.com/support/documentation/white_papers/wp370_Intelligent_Clock_Gating.pdf

https://www.doulos.com/knowhow/fpga/synchronisation/

 

[harpv]

Hi,

I believe your requirement can be rephrased as a dynamic clock mux without any glitches.

I'm posting couple of links here of such circuits. These are also essentially gating off one of the clock sources before switching. So I'm not sure if this matches your requirement.

http://www.eetimes.com/document.asp?doc_id=1202359

**broken link removed**