Implementaing an ASIC design on an FPGA

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I have designed an IP, which I want to implement on an FPGA for testing purposes. The design has been synthesized and meets all constraints. How do I find an FPGA that would have the required logic elements to fit this design. Is there some math that I can do to figure this out.

The area report for the IP shows a total cell area of 220407

Code: 
Combinational area:              53457.518967
Buf/Inv area:                     8234.146975
Noncombinational area:           88329.716581
Macro/Black Box area:            78619.300293
Total cell area:                220406.535841
 

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Required LEs = (Total cell area in square microns) / (LE area in square microns)
The LE area can vary depending on the FPGA architecture and technology node. You can find the LE area in the FPGA datasheet or documentation.
For example, if the LE area of the FPGA you are considering is 1.6 square microns, the estimated number of required LEs for your design would be:
Required LEs = 220407 / 1.6 = 137754
You can also estimate the required LUTs and FFs based on your design's combinational and non-combinational area. The number of LUTs and FFs required depends on the specific implementation of your design, so you would need to perform some analysis or simulation to determine these numbers accurately.
Once you have estimated the required FPGA resources, you can select an FPGA that has sufficient resources to accommodate your design. You can find the resource specifications for various FPGAs in their datasheets or documentation.
 
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I had considered DE2i-150 FPGA Development Kit. It uses Cyclone IV EP4CGX150DF31, and has 149760 LEs. I am not sure abut the "LE area" of this FPGA. The specification just list the 60nm. Will that be the LE area?
 

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I fear, comparison by area ignores the implementation differences between ASIC and FPGA. A straightforward way is to synthesize the IP in the FPGA tool (Intel Quartus).
 

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I'm not feeling that a FPGA "breadboard" is much better of a
"validation" than simple simulation results, embedding as it does
both topological and timing differences. Maybe if you need to
plug something up against a real world challenge-case.
 

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Unfortunately I do not have a straightforwatd answer or equation for conversion. Some years ago I tried to do a comparison and found the following results useful (I just copied the following from an old EDABoard thread of mine):

Gate equivalent is an ASIC terminology and not related to FPGAs. FPGAs are basically composed of LUTs, Flops and MUXes. It is difficult to make exact comparisons.

here are some resources to help you:

https://www.edaboard.com/showthread.php?380338-Comparing-ASIC-gate-equivalent-with-Xilinx-FPGA-LUTs
https://www.edaboard.com/showthread.php?22190-FPGA-LUT-to-ASIC-Gates

Here are some threads from Xilinx forums discussing the issue you have in mind.
http://forums.xilinx.com/t5/UltraSc...-ASIC-gate-equivalent-with-XU-LUTs/m-p/893795
http://forums.xilinx.com/t5/Other-F...ic-cell-equivalecny-with-ASIC-gate/m-p/855600


An old article from Synopsys:

Synopsys Blog | Latest Insights on EDA, IP & Systems Design

Explore Synopsys Blog for the latest insights and trends in EDA, IP, and Systems Design. Stay updated with expert articles and industry news.
blogs.synopsys.com
 
Last edited:

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FvM said:
I fear, comparison by area ignores the implementation differences between ASIC and FPGA. A straightforward way is to synthesize the IP in the FPGA tool (Intel Quartus).
Click to expand...
Yes, this. It also ignores the fact that people have been measuring LE or GE in different ways and your estimation can easily be off by 50%. Simplest answer is give it a try. Count LUTs/FFs instead of trying to find a conversion rule.
 

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