Implement sar control in pld , need example ???

[wls]

Hello . I need some example to implement fsm and verilog of Successive Approximate Register ( SAR ) , example 74C905 . Anyone did it before ?


Regards.

 

[nand_gates]

Check out this code!
Hope this helps!

module sar(
   // Outputs
   data, eoc, 
   // Inputs
   clk, start, gt
   );
   input clk;
   input start;
   output [7:0] data;
   output      eoc;
   input       gt;
   reg       eoc;
   reg [7:0]   data, data_nx;
   reg [7:0]   shift;
   always @(posedge clk or negedge start) begin
      if (!start) begin
         shift <= 8'b10000000;
         eoc <= 1'b1;
      end else begin
         shift <= {1'b0,shift[7:1]};
         eoc <= !(shift == 1);
      end
   end
   
   always @(negedge clk or negedge start) begin
      if (!start) begin
         data <= 8'b10000000;
      end else begin
         data <= data_nx;
      end
   end
   
   always @(data or gt or shift) begin
      data_nx = data;
      
      if (shift[7] & gt) 
        data_nx[7] = 1'b0;
      
      if (shift[6] & gt) 
        data_nx[6] = 1'b0;
      else if (shift[7])
        data_nx[6] = 1'b1;

      if (shift[5] & gt) 
        data_nx[5] = 1'b0;
      else if (shift[6])
        data_nx[5] = 1'b1;

      if (shift[4] & gt) 
        data_nx[4] = 1'b0;
      else if (shift[5])
        data_nx[4] = 1'b1;

      if (shift[3] & gt) 
        data_nx[3] = 1'b0;
      else if (shift[4])
        data_nx[3] = 1'b1;

      if (shift[2] & gt) 
        data_nx[2] = 1'b0;
      else if (shift[3])
        data_nx[2] = 1'b1;

      if (shift[1] & gt) 
        data_nx[1] = 1'b0;
      else if (shift[2])
        data_nx[1] = 1'b1;

      if (shift[0] & gt) 
        data_nx[0] = 1'b0;
      else if (shift[1])
        data_nx[0] = 1'b1;
   end
   
endmodule // sar

   
module test();
   reg         clk;  
   wire        gt;   
   reg         start;
   reg [7:0]   din;  
   

   wire [7:0]  data;
   wire        eoc; 

   assign      gt = data > din; // Analog comparator
 
   sar sar(
           // Outputs
           .data                        (data[7:0]),
           .eoc                         (eoc),
           // Inputs
           .clk                         (clk),
           .start                       (start),
           .gt                          (gt));

   initial begin
      $shm_open("WAVEFORM");
      $shm_probe(test,"AS");
      clk = 0;
      start = 1;
      din = 0;
      #44;
      repeat(255) begin
         @(negedge clk);
         start = 0;
         @(negedge clk);
         start = 1;
         repeat(10) @(negedge clk);
         din = din + 1;
      end
      #2000 $finish;
   end
   always #5 clk = ~clk;
endmodule // tests

Added after 51 minutes:

Here is one more Idea!

 

[wls]

Thx a lot nand_gates for the code and diagram.