implement a simple CPU using verilog code into altera DE2 board

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allyssa

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Hi,

i'm new here and still new in FPGA design. i hope this is the right place to post. i had tried an example to design a simple CPU from

https://www.edaboard.com/threads/110622/

actually i has no problem with the codes, it's compile successfully but i dont know how to implement this code into altera board DE2. i hope someone can help me. thanks in advance.
 

You need QuartusII software.
Install it
synthesis your code in quartusII
connect your board to your pc
select: tools -> programmer
and at last click program

Also you can read your "User Manual" of your board and also you can google it
 
i had already installed the quartussII and compiled the code. actually im a little bit confuse with the module RAM in this example.
How to implement RAM module into DE2 board?
Do i need to use SOPC builder to implement it?
sorry, im very beginner. please help me.
 

I can imagine clearer questions...

Are you talking about using FPGA internal RAM or interfacing external RAM of the development board?
You'll neither use the SOPC builder for this purpose, just write Verilog code.

I presume that ´the project already makes use of internal RAM, you'll see it in the compilation report.
 
i think im using internal RAM but im not very sure about this. from this example ( https://www.edaboard.com/threads/110622/ )
it is already given the verilog code for the RAM. that mean im using internal RAM, right?
and one more i dont have to use SOPC builder right?

im totally blur right now because im google and it said to use SOPC builder to use RAM in DE2 board.
 

The given Verilog may or may not use internal block RAM. I suggested to look at the compilation report to find out.
 
Probably an internal RAM is used. Can you please share your code of RAM?
 
i already attached the whole code for CPU but here is the RAM code

module RAM (Q,D,addr,we,clk);
input [7:0] D;
input [7:0] addr;
input we,clk;
output [7:0] Q;
wire high;

assign high=1;

lpm_ram_dq myRAM (.q(Q),.data(D),.address(addr),.we(we),.inclock(clk),.outclock(high));
defparam myRAM.lpm_width=8;
defparam myRAM.lpm_widthad=8;
defparam myRAM.lpm_indata="REGISTERED";
defparam myRAM.lpm_outdata="UNREGISTERED";
defparam myRAM.lpm_file="RAMtest.mif";


endmodule

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can u check for me whether it is internal RAM or not?
 

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  • simple CPU.zip
    4.4 KB · Views: 147

That's an Altera specific library module for internal RAM. It should always work with Quartus.
 

owh, i got it now. thanks u very much u guys are very helpful.

so, how im gonna implement it into DE2 board? just assign the pin assignment of top level module,
and run the program, right? dont have to use SOPC right?
 

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