Implement a serial transmission system

[love3cyou]

My teacher gave me a problem below :

Implement a serial transmission system, the system is described as following :
- The system is divided into 2 parts based on their function :
+) The first module receives data from users and send them to the second module through a single wire.
+) The second module receives data from the first module and processes the input data before showing results.
- The received data in module 2 are the binary value of two 3-bits unsigned numbers. These numbers then will be added together in the calculation’s process in module 2.
- Outputs of the system are presented by LED

Here is a circuit that I have designed and it doesn't work properly. Hope you guys find out the problem and point it for me T_T, I have thought back and forth but found nothing.

 

[TrickyDicky]

How did you produce this circuit? Heave you written a test bench to test it

 

[KlausST]

Hi,

If we should find the problem, then you need to give an error description first.

Klaus

 

[love3cyou]

Hi,

If we should find the problem, then you need to give an error description first.

Klaus

Okay, I should have given at first ^_^

+) The first module receives data from users and send them to the second module through a single wire.
+) The second module receives data from the first module and processes the input data before showing results.
+) These numbers then will be added together in the calculation’s process in module 2.

- I put the same clock pulse for 74LS164 and 74LS166.
- At 74LS166, I put input data first by using Switch. 74LS166 transfer data (serial out) to B in 74LS164 ((https://www.ti.com/lit/ds/symlink/sn54ls164-sp.pdf))
- In 74LS164, as A = VCC, whenever B is high, Q = 1.
For Example, if my input (D0->D7) = 00010001, then output at 74LS164 will be the same theoretically.
- These outputs go to 74LS83 (which is Full-Adder https://www.futurlec.com/74LS/74LS83.shtml) and add together, the rest of the circuit is BCD to 7-segment decoder.

The problem is 74LS164 can't hold these outputs, continue "pushing" it and D0->D7 = 00000000.

- - - Updated - - -

How did you produce this circuit? Heave you written a test bench to test it

I just following requirements given in the problem, and my teacher suggestions too ^_^
+) The first module receives data from users and send them to the second module through a single wire. = 74LS166
+) The second module receives data from the first module and processes the input data before showing results. = 74LS164
- The received data in module 2 are the binary value of two 3-bits unsigned numbers. These numbers then will be added together in the calculation’s process in module 2.= 74LS83

The rest of the circuit is BCD to 7-segment decoder

I have written it on CircuitMaker2000 and the problem is 74LS164 can't hold the output and keep "pushing" it. Therefore, these outputs are 0 respectively.

 

[FvM]

The problem is 74LS164 can't hold these outputs, continue "pushing" it and D0->D7 = 00000000.

Consider a latch or synchronous register if you want to see the result longer than one clock cycle.

I have more general problems with your circuit. How are the clock and control signals generated. You are apparently assuming, that the receiver has a "magic" clock, synchronous with the transmitter to sample each bit at the right time. Is this assumption substantiated by the problem description? In the general case, I would expect that the receiver needs to recognize a start time from the received data (like an UART does). Also generate a control sequence to register the received data word.

 

[KlausST]

Hi,

- I put the same clock pulse for 74LS164 and 74LS166.

This is not wired in your schematic. And ... does this fit to the "one wire" requirement?

How do you synchronize '164 and '166. I know in a simulation environment there is no risk to get out of sync, but in real world it will happen.
But maybe this does not need to be solved within your challenge...

These outputs go to 74LS83 (which is Full-Adder

The requirement is to add two 3-bit values... which gives a 4 bit result.

Your schematic shows to add two 4 bit values, which gives a 5 bit result. But it seems you ignore the carry bit.
I don't know whether this violates the requirement or not...

The problem is 74LS164 can't hold these outputs, continue "pushing" it and D0->D7 = 00000000.

This is a part of the synchronizing problem....mentioned above.

The P-->S shift register needs 8 clocks to shift the data. The same 8 clocks are needed to "receive" the data..

--> What about a counter that generates a "sync" pulse every 8'th clock. And add a DFF after the S-->P shift register to "hold" the data during transfer.
You may have a look at 74xx595 shift register which already includes such a DFF.

Klaus

 

[love3cyou]

You are apparently assuming, that the receiver has a "magic" clock, synchronous with the transmitter to sample each bit at the right time. Is this assumption substantiated by the problem description?

You are right. It make me easy for learning purpose since I am a beginner and the whole of my knowledge are "Digital systems principles and applications by Ronald J. Tocci" in a nutshell

In the general case, I would expect that the receiver needs to recognize a start time from the received data (like an UART does). Also generate a control sequence to register the received data word.
Thank you, this help me so much indeed ! I knew its function but forgot the name ^_^

 

[KlausST]

Hi,

that the receiver needs to recognize a start time from the received data (like an UART does)

I don't know about "start time" with a UART.
It usually uses STARTBIT and STOPBIT.

In most cases each of them is just one bit_time in length.

No other synchronizing method is needed in a random data bitstream.


Klaus

 

[love3cyou]

Hi,

The P-->S shift register needs 8 clocks to shift the data. The same 8 clocks are needed to "receive" the data..

--> What about a counter that generates a "sync" pulse every 8'th clock. And add a DFF after the S-->P shift register to "hold" the data during transfer.
You may have a look at 74xx595 shift register which already includes such a DFF.

Klaus

That is so helpful, thank you very much ^_^