Impedance Matching OR Impedance Transformation for switch mode RF PA?

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engrMunna

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Hi,
I am working with a simple class D RF PA targeting a centre frequency of 2.5GHz.(Bandwidth not the concern at the moment.) . So its basically an cmos-inverter driving a 50 ohm load. And I have added L and C in series in between the Load and the inverter output so that the resonance frequency of the series RLC is 2.5 GHz.

My question is that for such a configuration is it neccesary to have impedance matching network between the RLC series circuit and the inverter output? Because I read somewhere that for PAs we do "impedance transfromation" and not "impednace matching" ? Is that right?
 

Are you talking about a RF class D amp, or a PWM class D (actually class S) amp?

Impedance matching is a specific case of impedance transformation. For a SMPA, an impedance match at the PA output isn't optimal, rather you need to find the impedance that gives a good tradeoff between output power and efficiency.
 

Is there a difference? I mean a PWM at RF frequencies driving a Class D PA?
 

When I say PWM I mean you're synthesizing a waveform by modulating the duty cycle of a PWM carrier which is at a much higher frequency than the desired output carrier. This is often called a class D amp but class S is the more correct term. This isn't feasible at 2.5GHz, so I assume you mean the more classic Class D topologies which normally run at a fixed 50% duty cycle, and amplitude modulation is achieved by high level modulation (Kahn technique).
 

At this moment yes I am simulating it with a fixed 50% duty cycle, but later on I will drive the inveter/ PA with a 2.5GHz PWM (where the duty cycle will not be constant)...OK any ways I have found the answer to my original question in this thread....that for switzhed mode PA you cant do an small signal impedance matching....a better way would be to do a load - pull for large signal matching....
 

Load pull will always give the "real" answer, but ultimately if you want to maximize efficiency then you don't want to pursue an impedance match. In general for a voltage mode class D you will get good efficiency if the load impedance is significantly higher than the inverter output.
 

So the design method should be that I should transform the load resistance to some higher value as compared to the On resistance of NMOS or PMOS using impedance TRANSFORMATION and not impednace matching
 

Yes, that's the idea, but only rigorous analysis or experimentation (load pull) can really tell you exactly what impedance you want to transform to. Also consider that for SMPA, the impedance at harmonic frequencies impacts efficiency as well, but that's usually a much more difficult optimization which many people ignore.
 
OK thanks! Wel yes I have a series RLC circuit (with R = 50 ohm) tuned to my centre frequency....so that at the output in indeal conditions I get only the fundamental frequency sine wave (2.5Ghz in this case)....so that harmonic power dissapation is minimized.
 

See this thread about TI CC2520, a 2.4 GHz radio: https://e2e.ti.com/support/low_power_rf/f/155/t/16454.aspx
Is it a related type of problem?
According to that link should impedance matching at least for first harmonic be high impedance matched (reflective) as it affect TX efficiency. My practical tests with CC2520 shows that also. It can be a difference in the range up to 6 dB output power at 2.4 GHz for same power consumption depending how the circuit is matched at 4-5 GHz. Impedance matching at 2.4 GHz for finding best power efficiency is not any big problem but the combination of a matching that also result in low radiation level of harmonics can be very challenging, especially if working with unshielded matching network where inductors easily becomes antennas.
 

A particular aspect of Class-D (theoretically with infinitely fast switching) is that efficiency is not degraded too much by a reasonable mismatch in the load.
But to get the maximum output power, the PA needs a matching network at the output. You can try to integrate somehow the series LC resonator (on fundamental) into the output matching circuit.
 

Well the CC2520 is a different situation because it's a transceiver port, and therefore the matching network has to be designed with both TX and RX performance in mind. It's likely that their reference matching network gives a tradeoff between the two (probably favoring RX performance).

Conjugate matching will give you higher maximum power output, but at the cost of efficiency. Without knowing more about the OP's application it's hard to advise one way or the other, but in general efficiency is the main point of class D.
 

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