If the delay time on the track length is more than 1/3 to 1/6 of the rise time, then you can expect overshoot from mismatched transmission line impedance and load. The track width to height (w/h) above ground plane dominates complex math for low impedance. so lower h or wider w reduces impedance. CMOS technology determines ESR or RdsOn of drivers, which are typically 50 Ohms to 25 Ohms for ALV type 2.
PECL always uses controlled impedances due to rise time.
Vp = c/√(μ*εr) depending on dielectric Vp= 1/2 to 2/3 *c typ.
where c= 3e8m/s or Vp = 1.5 to 2 e8 [m/s] or 150 to 200 mm/ns
Using a 3x rule of thumb , this reduces ... 50 to 66 mm/ns of rise time.
USing a 6x RUle of thumb, this reduces ... 25 to 33 mm per ns of rise time on your Flip Flop outputs.
The reason for concern on FF is for reasons of lowest latency the outputs are internally fed back, so any transient spikes or ripple may cause false operation and should be buffered, which can be controlled with load and/or transmission line impedances and if not, buffered for external signals that may get crosstalk.
So with slow Rise/fall time, the tolerance on length is wide.
This is from my quick calculations.... not old memories.