Impact of Current loading for voltage multiplier

Hi,

Can you please let me the impact of current loading for the attached circuit?
The attached circuit is a 4-stage dc-dc converter- charge pump.
When I give an input voltage of 1V, the output voltage is around 4.6 V using cadence simulations. The expected output voltage is 5V.
I am able to understand and see the increase in the output voltage from stage to stage.
But I am unable to understand the impact the current loading.

I have attached the circuit and the plots which I got.

Can you please let me know the effects of current loading of the above circuit?

Assuming your circuit works the same as typical diode-and-capacitor voltage multipliers...

When no load is attached, all capacitors quickly charge to their maximum volt level. Then current stops. Charge-pump action ceases.

With a load attached, it draws down the output capacitor. This draws down the preceding capacitor. Etc. The initial charge-pump capacitor resumes its action of alternately charging and discharging. All the capacitors do likewise.

Volt level on the load declines. This is because some energy is subtracted by charge/discharge action.

I have a Youtube video portraying a charge-pump doubler as an animated simulation.

It depicts capacitors charging and discharging. It depicts current bundles traveling through wires.

https://youtu.be/3czj7J_FE_k

At first sight, the "effects of current loading" would be described as an internal resistance. It's existence shouldn't be too surprizing.

If you look for the details, you'll notice, that capacitors and switch resistance are both affecting it, depending on switching frequency to RC relation, either one or the other will dominate. Needless to say that cadence can help you to find out the exact behaviour.

The presented circuit is a somehow unusual voltage multiplier, as a confusing point, most of the input power is actually supplied by the clock source. Don't know how it's modelled in your setup.

FvM said:

At first sight, the "effects of current loading" would be described as an internal resistance. It's existence shouldn't be too surprizing.

If you look for the details, you'll notice, that capacitors and switch resistance are both affecting it, depending on switching frequency to RC relation, either one or the other will dominate. Needless to say that cadence can help you to find out the exact behaviour.

The presented circuit is a somehow unusual voltage multiplier, as a confusing point, most of the input power is actually supplied by the clock source. Don't know how it's modelled in your setup.

Click to expand...

FvM,

we have modelled this circuit for RFID applications. We want to use the same in combination with a rectifier.
Can you please brief me why you called this as a unusual voltage multiplier?
I had simulated the circuit using the input and clock voltages as same. Tried the circuit simulation from 0.7V to 2V.
Its giving output voltage in a nicer way. But still, I am unable to realize the impact of current loading.
I am novice to this concept. Request you to please explain the same in an understandable format as I have a presentation tomorrow.

I had simulated the circuit using the input and clock voltages as same. Tried the circuit simulation from 0.7V to 2V.

Click to expand...

This can't be seen from your simulation cicruit. Also the driver impedance of nets clk1 and clk2 is unspecified although they affect the output voltage.

But still, I am unable to realize the impact of current loading.

Click to expand...

What's your particular problem with it? A voltage multiplier must have an output resistance, thus show a load dependent voltage drop, isn't it?