Imaging pipeline ADC redundancy from averaging perspective

Hello,I have heard a theory where the digital correction redundancy method, where we add an shift to the left is basicly doing a sum and dividing by 2 which making avarage of two numbers and their avarage will bring us closer to the real result.
But why when we have one redudant stage which comes after another redundant stage then their digital output should be considered the same data?(which requires avaraging to get more accurate result)


For example given the situation shown bellow where we have 1.5bit->1.5bit->2bit
first stage gived us b5b4
seconds stage gives us b3b2
third stage gives us b1b0
What bits do we consider to represent the same data?
Those bits came from different stages.next stage gets different "input"(residue)
Binary avarage is implemented as avg = (x & y) + ((x ^ y) >> 1);

why are we doing avarage "a" and "b" in the first place. "a" is the output of the first 1.5bit redundant stage ,"b" is the output of the second redundant stage. Why they represent the same Data?
I cant see it here in the table bellow.
Thanks