Image Encryption & Decryption using VHDL

Status
Not open for further replies.
M

Manish29101991

Newbie level 6
Joined
Jan 31, 2013
Messages
11
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
India
Visit site
Activity points
1,364
Hello brother/sister..!!
can anyone please mail me the coding for "image encryption and decryption in VHDL". I have got this as my graduation project. I will be very thankful if you provide me with the coding and guide me in the project. Hoping for your early reply.
 

I have done the coding for data encryption & decryption (AES-128) in VHDL. But i am confused how to convert an image to 128 bit data. Please help me.
 

We are all confused about something. More specifics, less generic cries for help please. By which I mean, take some time to explain what you have so far and what your specific design requirements are.
 

are we talking simulation? synthesis? bitmap? text? jpg?

Like mrflibble said - give us better questions, you'll get better answers.
 

To mrflibble & TrickyDicky
I have done the coding for data encryption & decryption using AES-128 bit in VHDL. Now i want to advance my project to image encryption and decryption (where image is in .jpeg format) using AES-128.
One way i thought to convert the image to 128 bit data so that i can feed this data in AES-128 algorithm to encrypt & decrypt the image.
Is this method correct ? If yes then please guide me how to proceed or else if you have some new alternative then suggestions are heartly welcome.
 

you wouldnt want to use jpg - it has things like file headers and compression that would be a pain in the backside to take apart in an FPGA. best to let a processor do that and then feed you the raw data.
 

I must admit, I don't exactly understand the problem. AES-128 means that the data uses a fixed block size of 128 bits. The data file can have any size starting from 1 bit upto to Megabytes. It's split into 128 bit blocks and the last block is filled up.

This way you can compress any image format, e.g. JPEG. You didn't mention that coding and decoding of the jpg data is also involved with the project.
 

To TrickyDicky & FvM & to everyone
See i have completed my minor project as "DATA ENCRYPTION & DECRYPTION in VHDL". Here i have adopted AES-128 algorithm. I have completed the coding for the same in VHDL using Xilinx ISE Design Suite 13.2. Finally simulated behavioral model in ISim simulator and 128 bit data has been successfully encrypted & decrypted.
Now i want to advance my minor project to major project.
My major project is "IMAGE ENCRYPTION & DECRYPTION in VHDL". Please help me how to proceed.???
 

AES-128 doesn't care what the data it's working on is. You don't have to convert JPEG to anything else - just split it into 128-bit chunks.
 

There are lots of ways to do it, but it will depend entirely on your application and without more information we cannot possibly help you. Is data loaded into the AES module in 128-bit words, serially, or something in between? Are you storing the JPEG data in a ROM in your FPGA/ASIC or is it being input to the device, and if so, is the input serial or parallel?

This is systems engineering - you need to join a few different blocks together, and it's your job to come up with the glue that holds it all together. That's why we get paid the big bucks!
 

mrflibble said:
By reading a book on vhdl. Seriously.
Click to expand...
...and let's not forget to read a book on digital design too. The questions you've posed are very basic ones in digital design and architecture. Seriously, if you can't come up with at least a couple of solutions to break data into 128-bit chunks you need to either go back and re-learn the basics or change fields to something that fits your strengths.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…