Goran Dakov
Newbie level 5
I'm open sourcing the instruction set of my cpu. The ISA is a vliw/risc hybrid, where the "small" instructions are variable width, packed in a bundle. They do not cross a bundle. Sizes multiples of 16-bit, last 16 bit of a 256-bit bundle are "stop" bits for each instruction. This is to ease making a wide frontend. Although fetch width of less that 32 bytes is impossible, the predecoder and decoder can be decoupled by an instruction queue, so it is not a requirement that an implementation can dispatch a full bundle in one go.
Supports low-fat pointers (hopefully US 3-letter agencies don't have a generic patent on that).
Supports low-fat pointers (hopefully US 3-letter agencies don't have a generic patent on that).